Traffic shaping ATM network switch

ABSTRACT

An ATM network switch includes a switch fabric (14), and a plurality of slot controllers (11) coupled to the switch fabric. Each slot controller has at least one external data link (12, 13), cell receiving circuitry (21) for receiving ATM cells from the data link and cell transmitting circuitry (22) for transmitting ATM cells outwardly on the data link. The cell transmitting circuitry of each slot controller includes traffic shaping circuitry (23) arranged to set, for each cell presented to the transmitting circuitry, a current onward transmission time where onward transmission at the input rate meets a predetermined flow rate criterion, and a delayed onward transmission time where onward transmission at the current time would cause the traffic on a VC to exceed a predetermined flow rate criterion. The traffic shaping circuitry includes a buffer (24) which stores each new cell at an address corresponding to the onward transmission time, and output logic (32 or 44) for outputting cells from the buffer at a time corresponding to the address thereof.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to an asynchronous transfer mode (ATM) networkswitch. More particularly, this invention relates to a switch havingmeans for controlling the flow of ATM cells constituting an individualvirtual connection (VC).

2. Background of the Invention

In ATM data transmission, cells of data conventionally comprisingfifty-three bytes (forty-eight bytes carrying data and the remainingfive bytes defining the cell header, the address and relatedinformation) pass through the network on a virtual connection at anagreed upon rate related to the available bandwidth and the level orservice paid for. The agreed upon rate will relate not only to thesteady average flow of data, but will also limit the peak flow rates.

Over an extensive network, cells on a connection can become bunchedtogether with different cells having different delays imposed upon themat different stages, so that the cell flow on a VC then does not conformwith the agreed upon rates. To prevent rates being exceeded to thedetriment of other VC's in the network, the network will include, forexample at the boundary between different networks, means for policingthe flow. The flow policing means typically includes a "leaky bucket"device which assesses the peak and average flow rates of cells on a VCand if required either downgrades the cells' priority or discards cells.An example of such a device is disclosed in co-owned UK PatentApplication No. 9505358.3 which is hereby incorporated herein in itsentirety. Since policing can result in the discarding of cells whichshould not be discarded, it is desirable to effect "traffic shaping" tospace out the cells on a VC sufficiently so as to ensure that they meetthe agreed upon rates, and in particular the peak rates.

A problem with traffic shaping is that it is desirable to delay thetransmission of cells by variable amounts in an attempt to avoid cellloss. In practice, however, variable cell delay has been difficult toimplement.

SUMMARY OF THE INVENTION

It is therefore an object of the invention to provide a traffic shapingmeans for an ATM switch.

It is another object of the invention to provide an ATM switch with atraffic shaping mechanism which delays the transmission of incomingcells by varying amounts of time.

It is a further object of the invention to provide a traffic shapingmechanism for an ATM switch which accounts for both peak and averagecell flow rates.

In accord with the objects of the invention, an ATM network switch isprovided with a traffic shaping means on the input or output sidethereof. The traffic shaping means broadly comprises means fordetermining for each cell received at the traffic shaping means anonward transmission time dependent upon the time interval between thearrival of the cell and the time of arrival of the preceding cell on thesame VC, buffer means for storing each new cell at an addresscorresponding to the onward transmission time, and means for outputtingcells from the buffer means at a time corresponding to the addressthereof.

In one embodiment of the invention, the switch comprises a cross-pointswitch (switch fabric) having a plurality of input ports (cell receivingmeans for receiving ATM cells from a data link) and a plurality ofoutput ports (cell transmitting means for transmitting ATM cellsoutwardly on the data link), and one or more controllers (which areoften called "slot controllers" or "link controllers") for switchingdata cells from any input port to any output port. The cell transmittingmeans of each controller includes the traffic shaping means arranged toset, for each cell presented to the transmitting means, a current onwardtransmission time when onward transmission at the input rate meets apredetermined flow rate criterion, and a delayed onward transmissiontime when onward transmission at the current time would cause thetraffic on a VC to exceed a predetermined flow rate criterion. Thetraffic shaping means comprises at least one leaky bucket processor fordetermining an onward transmission time, buffer means for storing eachnew cell at an address corresponding to the onward transmission time,and means for outputting cells from the buffer means at a timecorresponding to the address thereof.

In a preferred embodiment, each leaky bucket processor of the trafficshaping means comprises:

a timer means for timing the arrival of each ATM cell presented to thetransmitting means;

memory means for storing a predetermined regular bucket increment, acurrent bucket level value and a bucket maximum value, being the maximumcapacity of the bucket;

calculating means for calculating the time difference between thearrival time of the cell and a stored onward transmission time for thepreceding cell on the same VC, and for calculating a new bucket levelfrom the time difference, the current bucket level, and the bucketincrement;

subtraction means for subtracting the maximum level from the new levelto give an overflow value and, if the overflow value is negative, forsetting the value of the overflow to zero; and

means for adding the overflow value to the current time to give theonward transmission time for the cell and for storing the onwardtransmission time in the memory or buffer means.

According to a preferred arrangement, the traffic shaping meanscomprises a leaky bucket processor which carries on two leaky bucketcalculations, and means for comparing the overflow values calculated inthe two leaky bucket calculations and for passing only the greater ofthe two values to the adding means. Preferably, a first of the two leakybucket calculations monitors peak cell flow rates, while the secondleaky bucket calculation monitors average cell flow rates.

According to another preferred aspect of the invention, the buffer meanscomprises a FIFO for each VC for storing cells on that VC, and memorymeans for storing at an address corresponding to the onward transmissiontime for each cell the address of the cell. The buffer means is suitablyconfigured dynamically in Random Access Memory (RAM), so that the VCFIFOs are set up as new VCs are set up. Also, the output means ispreferably arranged to output cells from the FIFOs in accordance withthe data stored in the memory means.

Additional objects and advantages of the invention will become apparentto those skilled in the art upon reference to the detailed descriptiontaken in conjunction with the provided figures.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a representation of an ATM switch in accordance with theinvention;

FIG. 2 is a more detailed representation of one of the slot controllersof the switch shown in FIG. 1;

FIG. 3 is a representation of the buffer memory arrangement forming partof the traffic shaping means within the slot controller shown in FIG. 2;

FIG. 4 is a representation of an alternative buffer arrangement whichcan be used with the traffic shaping means within the slot controllershown in FIG. 2; and

FIG. 5 is a flow diagram of the leaky bucket algorithm used in thetraffic shaping means shown in FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, an ATM network switch is shown comprising aplurality of slot controllers 11a-11f and two separate switch fabrics14a and 14b. In the simple arrangement illustrated, six slot controllersare shown, but a typical switch might have sixteen slot controllers.Each slot controller 11 has an external input link 12 and output link13. The switch fabrics 14a and 14b are of a dynamic crosspoint type withinput and output connections 15 and 16 respectively to each of the slotcontrollers 11. This type of arrangement is described in more detail inco-owned application #GB9507454.8 which is hereby incorporated byreference herein in its entirety. The structure of the slot controllersis, for example, of the general type described and claimed in previouslyincorporated patent application #GB9505358.3, and ATM cells arriving ona input link 12 may be processed in the general manner described in thatapplication.

FIG. 2 shows the structure of a slot controller 11 in more detail. Inaccord with the preferred embodiment of the invention, the slotcontroller 11 comprises an input cell processor 21, whose structure willnot be described further since it has no bearing on the presentinvention. The input cell processor 21 is connected to the input link 12and to the input connections 15 to the switch fabric. Cells output fromthe switch fabric on connections 16 are processed for the transmissionon the output link 13 by an output cell processor 22 which includes aleaky bucket processing means 23 and a buffer memory 24. It is notedthat in FIG. 2, for the sake of clarity, only those components whichrelate to traffic shaping functions are illustrated. It will beappreciated, however, that the output cell processor 22 handlesadditional functions such as the writing to the cell headers of the newVPI/VCI information, and output to the output link 13.

As previously mentioned, the output cell processor 22 comprises a leakybucket processing means 23 and a buffer memory 24. The leaky bucketprocessing means 23 receives cells arriving from the switch fabric anddetermines for each cell, as hereinafter described with reference toFIG. 4, whether the peak and sustained cell flow rates appropriate tothe cell's VC have been exceeded. If the cell conforms with the peak andsustained flow rates specified, the cell is entered into a buffer memory24 at an address corresponding to the current time. If one or the otherof the peak and sustained rates has been exceeded, so that the leakybucket overflows, the amount of the overflow, or of the greater of theoverflows if both buckets overflow, is added to the current time as theaddress for the cell in the buffer memory 24. Thus, the onwardtransmission of the cell is delayed by the amount of the overflow, toensure that the cell will conform with the specified rates. The cellsare output from the buffer memory 24 in order of stored time slot; i.e.,the cells are not transmitted onwards before the relevant time slotbecomes due.

FIG. 3 shows a first arrangement of the buffer memory 24 forming part ofthe traffic shaping means in the slot controller illustrated in FIG. 2.In the arrangement of FIG. 3, the buffer memory 24 comprises amulti-dimensional FIFO 31 dynamically configured in Random Access Memory(RAM). For convenience of illustration, only a very small portion of thebuffer is shown in FIG. 3. The horizontal direction in the bufferrepresents different time slots arranged sequentially, the buffer beingsuch that the current time pointer moves along the buffer until itreaches one end, and is then reset to the other end so that the bufferis effectively "circular". At each time slot, one or more ATM cells maybe stored. The time slot may be empty if no cells are assigned the sameonward transmission time. If more than one cell is assigned the sameonward transmission time, the time slot is treated as a FIFO memory,with the cells being written to the slot sequentially and read out ofthe time slot in the same order in which they are written to the slot.An output logic means 32 is arranged to step a current time pointeralong the buffer according to the actual current time, but to controloutput of cells according to an output time pointer which lags behindthe current time by up to approximately eight time slots (the algorithmattempts to maintain a maximum of eight time slots lag, but if manycells are present a grater lag can sometimes develop). Conveniently, thetime slots are each of 640 ns duration, being thirty-two clock periodsof the system clock. In a convenient mode of operation, the outputpointer waits until the current clock has advanced by eight slotsrelative to the output time, and then during the next time intervallooks at each of the eight time slots to output the cells found. Thus,for the example shown in FIG. 3, the time slot b has three cellsawaiting transmission, and these are transmitted in turn. The next slot,c might for example have no cells waiting, so the output time pointerjumps to the next slot d and causes the two cells waiting there to betransmitted in turn. If all the waiting cells in the eight slots havenot been transmitted in the next time interval of 640 ns, the outputtime pointer continues to advance at eight-times the clock speed untilit "catches up" and cells are being transmitted within the appropriatetime interval. In practice, it is expected that the set of eight slotswill allow the output to keep pace with the current time, but it will beappreciated that different numbers of slots, with appropriate speeds,may be selected if desired or if necessary.

FIG. 4 illustrates an alternative arrangement for the buffer part of thetraffic shaping means, in which the cells are stored in a series ofFIFOs 41 defined dynamically in RAM, each VC having its own FIFO, and abuffer memory 42 stores at appropriate time slot addresses the addressof the relevant FIFO 41. Leaky bucket processing logic 43 is used toprocess incoming cells in the manner hereinbefore described withreference to FIG. 2, and as further described hereinafter with referenceto FIG. 5. In a manner analogous to that described with reference toFIG. 3, the buffer memory 42 is controlled by logic 44 to store insequential time slots the addresses of the cells in the FIFOs 41 insteadof the actual cells, and to output the addresses in sequence to causethe cells to be output from the FIFOs 41. More than one address can bestored at any time slot, and the addresses are then output in sequenceon a "first in first out" basis, in the same way as the actual cells areoutput in the embodiment described with reference to FIG. 3.

FIG. 5 illustrates the algorithm used by the leaky bucket processor. Thealgorithm shown uses two buckets, one for peak flow and one forsustained flow, and each cell is process by both buckets, the result ofthe bucket having the greatest overflow being used to determine the timeslot for the cell address (for the embodiment shown in FIG. 4) or (inthe case of the system illustrated in FIG. 3) the time slot in the FIFOfor the cell itself. The new cell is received at 50 to start theprocess. At 51, the algorithm calculates the time interval between thestored onward transmission time for the last cell on the same VC and thecurrent time at which the new cell arrives. Then the new level of eachbucket is determined at 52 by subtracting the calculated time intervalfrom the existing bucket level, and the new level is used to calculateat 53 an overflow value by subtracting the bucket maximum from the newlevel. If it is determined at 54 that the overflow is negative, at 55the overflow is set to zero. Regardless, the overflow values obtainedfrom the two buckets (peak and average) are compared and the greatestoverflow is selected at 56. At 57, the onward transmission time for thecell is set to the current time plus the amount of the overflow. Eachbucket level is then incremented at 58 by the stored predeterminedincrement, which is equivalent to one cell, and the new bucket levelsare written at 59 to the memory. The stored time is then set to theonward transmission time at 60 for use in the calculation for the nextcell on the particular VC, and at 61 the system is ready to read thenext cell on the VC.

The resulting transmission time from the performance of the algorithm isused to set the time slot in the buffer memory at which the cell (in thecase of the embodiment is described with reference to FIG. 3), or thecell FIFO address (in the case of the embodiment described withreference to FIG. 4) is stored. The cell, or the address, then remainsin the appropriate time slot until the output time pointer determinesthat its contents should be read and the cell output, either directlyfrom the buffer, or, in the case of the FIG. 4 embodiment, from theseparate FIFO 41. The result of this operation is that the cells aretransmitted onward from the slot controller in a more controlled manner,with the effects of bunching of the cells having been removed.

There have been described and illustrated herein a traffic shaping ATMnetwork switch. While particular embodiments of the invention have beendescribed, it is noted intended that the invention be limited thereto,as it is intended that the invention be as broad in scope as the artwill allow and that the specification be read likewise. Thus, whileparticularly preferred processor apparatus disclosed in co-ownedapplications was described, it will be appreciated that other processorapparatus could be utilized in accord with the principles of theinvention. Likewise, while processing of two leaky buckets for peak andaverage flow rates was described, it will be appreciated that the leakybucket processor could process any number of leaky buckets. It willtherefore be appreciated by those skilled in the art that yet othermodifications could be made to the provided invention without deviatingfrom its spirit and scope as so claimed.

I claim:
 1. An ATM switch, comprising:traffic shaping means forregulating outgoing transmission of ATM cells from said ATM switch, saidtraffic shaping means comprisingmeans for determining an onwardtransmission time for each ATM cell received at said traffic shapingmeans, said onward transmission time being dependent for each ATM cellupon a time interval between a first time of arrival of a particular ATMcell on a virtual connection (VC) and a second time of arrival of theATM cell which preceded said particular ATM cell on said VC, buffermeans for storing each said ATM cell received at an addresscorresponding to said onward transmission time determined for that ATMcell, and means for outputting from said buffer means each of said ATMcells at times corresponding to the addresses of said buffer meanswhereinsaid means for determining an onward transmission time comprisesa leaky bucket processor havingtimer means for timing the arrival ofeach ATM cell presented to the said traffic shaping means, memory meansfor storing a predetermined regular bucket increment, a current bucketlevel value, a bucket maximum value, and an onward transmission time forthe previous cell on a given VC, calculating means for calculating thetime difference between the arrival time of the cell and the storedonward transmission time for the preceding cell on the same VC, and forcalculating a new bucket level from the time difference, the currentbucket level, and the bucket level increment, subtraction means forsubtracting the maximum level from the new level to give an overflowvalue and, if the overflow value is negative, for setting the value ofthe overflow to zero, and adding means for adding the overflow value tothe current time to give the onward transmission time for the cell andfor storing said time in the memory means.
 2. An ATM switch according toclaim 1, wherein:said leaky bucket processor monitors for a VC both apeak cell flow rate and an average cell flow rate, and said leaky bucketprocessor includes means for comparing overflow values calculated forsaid peak cell flow rate and said average cell flow rate by saidsubtraction means, and for passing only the greater of said overflowvalues to said adding means.
 3. An ATM switch according to claim 1,wherein:said buffer means comprises a FIFO for each VC for storing ATMcells on that VC, and memory means for storing at an addresscorresponding to the onward transmission time for each cell the addressFIFO containing the cell, and the output means is arranged to outputcells from the FIFOs in accordance with the data stored in the memorymeans.
 4. An ATM switch according to claim 3, wherein:said buffer meansis configured dynamically in Random Access Memory (RAM), whereby the VCFIFOs are set up as new VCs are set up.
 5. An ATM network switch,comprising:a) a plurality of controllers, each controller having cellreceiving means for receiving ATM cells from a data link and celltransmitting means for transmitting ATM cells outwardly on said datalink; b) a switch fabric means coupled to said plurality of controllers,said switch fabric means for switching a cell received from one of saidplurality controller to a selected one of the other of said plurality ofcontrollers for transmission on the external data link connectedthereto, whereineach cell transmitting means of each slot controllerincludes traffic shaping means arranged to set, for each cell presentedto the cell transmitting means, a current onward transmission time whereonward transmission at the input rate meets a predetermined flow ratecriterion, and a delayed onward transmission time where onwardtransmission at the current time would cause the traffic on a VC toexceed a predetermined flow rate criterion, said traffic shaping meanscomprising buffer means for storing each new cell at an addresscorresponding to the onward transmission time for a particular cell, andmeans for outputting cells from the buffer means at a time correspondingto the address thereof, whereinsaid traffic sharing means comprises aleaky bucket processor havingtimer means for timing the arrival of eachATM cell presented to the said traffic shaping means, memory means forstoring a predetermined regular bucket increment, a current bucket levelvalue, a bucket maximum value, and an onward transmission time for theprevious cell on a given VC, calculating means for calculating the timedifference between the arrival time of the cell and the stored onwardtransmission time for the preceding cell on the same VC, and forcalculating a new bucket level from the time difference, the currentbucket level, and the bucket level increment, subtraction means forsubtracting the maximum level from the new level to give an overflowvalue and, if the overflow value is negative, for setting the value ofthe overflow to zero, and adding means for adding the overflow value tothe current time to give the onward transmission time for the cell andfor storing said time in the memory means.
 6. An ATM switch according toclaim 5, wherein:said leaky bucket processor monitors for a VC both apeak cell flow rate and an average cell flow rate, and said leaky bucketprocessor includes means for comparing overflow values calculated forsaid peak cell flow rate and said average cell flow rate by saidsubtraction means, and for passing only the greater of said overflowvalues to said adding means.
 7. An ATM switch according to claim 5,wherein:said buffer means comprises a FIFO for each VC for storing ATMcells on that VC, and memory means for storing at an addresscorresponding to the onward transmission time for each cell the addressFIFO containing the cell, and the output means is arranged to outputcells from the FIFOs in accordance with the data stored in the memorymeans.
 8. An ATM switch according to claim 7, wherein:said buffer meansis configured dynamically in Random Access Memory (RAM), whereby the VCFIFOs are set up as new VCs are set up.
 9. An ATM switch, comprising:a)a switch fabric means for switching ATM cells; b) a plurality of inputdata links and output data links coupled to said switch fabric; and c) aplurality of traffic shaping means coupled to said switch fabric and tosaid output data links for regulating outgoing transmission of ATM cellsfrom said ATM switch, each said traffic shaping means comprisingi) meansfor determining an onward transmission time for each ATM cell receivedat said traffic shaping means, said onward transmission time beingdependent for each ATM cell upon a time interval between a first time ofarrival of a particular ATM cell on a virtual connection (VC) and asecond time of arrival of the ATM cell which preceded said particularATM cell on said VC, ii) buffer means for storing each said ATM cellreceived at an address corresponding to said onward transmission timedetermined for that ATM cell, and iii) means for outputting from saidbuffer means each of said ATM cells at times corresponding to theaddresses of said buffer means whereinsaid means for determining anonward transmission time comprises a leaky bucket processor havingtimermeans for timing the arrival of each ATM cell presented to the saidtraffic shading means, memory means for storing a predetermined regularbucket increment, a current bucket level value, a bucket maximum value,and an onward transmission time for the previous cell on a given VC,calculating means for calculating the time difference between thearrival time of the cell and the stored onward transmission time for thepreceding cell on the same VC, and for calculating a new bucket levelfrom the time difference, the current bucket level, and the bucket levelincrement, subtraction means for subtracting the maximum level from thenew level to give an overflow value and, if the overflow value isnegative, for setting the value of the overflow to zero, and addingmeans for adding the overflow value to the current time to give theonward transmission time for the cell and for storing said time in thememory means.
 10. An ATM network switch according to claim 9,wherein:said plurality of traffic shaping means are included within aplurality of controller means, each said controller means forcontrolling presentation of said ATM cells to said switch fabric means.